Robert's SIA Roadmap

Introduction

The following tables outline predictions of the Semiconductor Industry Association which represents the $60 billion chip manufacturing industry in the United States. In 1995, the the worldwide chip industry produced $154 billion in products with a projected increase $232 billion by 2000. From 1994 to 1995 worldwide sales of microprocessors increased 35% to 80 million units worth $12.7 billion. A reasonable decline in the growth rate of microprocessor sales to around 15% per annum would lead to the production of approximately a billion microprocessors in the year 2010.

The U.S. semiconductor industry spent 13% of their revenues, $5 billion, on research and development in 1995. If these figures are representative of foreign companies and extrapolated to 2000, the worldwide R&D expenditures by chip manufacturers should exceed $30 billion.

The market size and R&D expenditures are the drivers for the following projections.  The motivation is the need to keep Moore's Law valid.  (Would you want to be the CEO of Intel, AMD or IBM having to announce to shareholders that Moore's Law was going to break while you were "on the job"?).


Update (3 Dec 2001):

 
2000/2001 SIA Roadmap Summary
Year Unit 1993 1995 1999 2001 2003 2005 2008 2011 2014 2016
Feature Size
microns/nm
0.50
0.35
180
130
100
80
70
50
34
22
Internal Clock 
(high performance)
 Mhz/Ghz
200
300
750
1.68
2.31
5.17
6.74
11.5
19.3
28.7
Logic transistors 
million/cm2
2
4
6.6
13
24
44
109
269
664
 
Microprocessor
million
transistors/chip
5.2
12
23.8
47.6
95.2
  190
539
1523
4308
 
DRAM size 
Mbit/Gbit
16
64
256
512
 1
2
6
16
48
 
SRAM size
Mbit/Gbit
1
4
16
64
256
  
 
 
 
 
Voltage
Vdd
5
3.3
2.5
1.2
1.0
0.9
0.7
0.6
0.5
0.4 

 
1997 SIA Roadmap Summary
Year Unit 1993 1995 1998 2000 2003 2007 2010 2013 [1] Notes
Feature Size
microns
0.50
0.35
0.25
0.18
0.13
0.10
0.07
0.05
[2,9,10]
Internal Clock 
(high performance)
 Mhz/Ghz
200
300
750
1
1.5
 
 
 
[3,4,8,11]
Logic transistors 
million/cm2
2
4
7
13
25
50
90
150
[8]
Microprocessor
million
transistors/chip
5.2
12
4?
?
18
350
800
 
 
DRAM size 
Mbit/Gbit
16
64
256
1
4
16
64
256
[5,6]
SRAM size
Mbit/Gbit
1
4
16
64
256
1
4
8
[7]
Voltage
Vdd
5
3.3
2.5
1.8
1.5
1.2
0.9
0.9
 
1994 SIA Roadmap Summary
Year
Unit
 1993 1995 1998 2001 2004 2007 2010 2013 [1] Notes
Feature Size 
microns
0.50
0.35
0.25
0.18
0.13
0.10
0.07
0.05
[2]
Internal Clock 
(high performance)
Mhz/GHz
200
300
450
600
800
1
1.1
1.2
[3,4]
Logic transistors
million/cm2
2
4
7
13
25
50
90
150
 
Microprocessor million
transistors/chip
5.2
12
28
64
150
350
800
 
 
DRAM size
Mbit/Gbit
16
64
256
1
4
16
64
256
[5,6]
SRAM size
Mbit/Gbit
1
4
16
64
256
1
4
8
[7]
Voltage
Vdd
5
3.3
2.5
1.8
1.5
1.2
0.9
0.9
 

Notes:

  1. The figures from 2013 are from the 1993 Petaflops workshop extrapolations of the 1992 SIA technology projections. [GH]
  2. The path from 0.13 microns to 0.07 microns requires the use of ArF and F2 excimer lasers. In 1995, the path to feature sizes below 0.07 microns was unclear [SS].  But in the March, 1999 issue of European Semicondcutor by Lucent and SEMATECH may indicate that it may be possible go down to 0.05 um using photolithography and 126nm lasers. The path below ~0.07-0.05 microns is likely to use Extreme Ultraviolet Lithography [EUVL]
  3. Clock rates increase at a rate of 1.5 every 3 years. [GH]
  4. In July 1996, the DECAlpha 21164 was clocked at at 500 MHz. The 15.2 million transistor, Alpha 21264 in 0.28 mm fabrication technology was supposed to operate at 750 MHz in 1998.  In December of 1998, IBM was demonstrating 1GHz PowerPC microprocessors with > 1M transistors using 0.25 mm fabrication technology.
  5. DRAM capacity increases by a factor of 4 every 3 years with a cost increase of only 2.75. [GH]

    6. Recent news regarding Samsung 1Gbit DRAM would appear to indicate that the period may now 2 years.
  6. In December 1996, Samsung announced the demonstration of The first 1Gbit DRAM using 0.18-micron design rules, operating at 2.0V. Availability is expected after the year 2000.
  7. In December of 1996, Texas Instruments announced The development of TSRAMs which should diminish GaAs SRAM cell size by a factor of 10 and reduce power consumption by a factor of 200. Application of these technologies to silicon is being undertaken.
  8. In September 1997, IBM announced its Copper Metalization for Chips technology in SA-27 gate arrays which could run at 1.8 V, 1 GHz clock speeds, .12 mm effective channel length and support 150-200 milllion transistors (12 million gates) per chip.  These numbers provide chips projected for 2001-2004 3-5 years ahead of projections!
  9. Field Effect Transistors (FETs) were built in 1996 with a channel width of 0.1 mm as part of the EUVL effort [EUVL].  (This would be 10 years ahead of the projected times for these chips).
  10. A CNET news article from August 6, 1998 indicated that Intel would adopt 0.13 mm technology and copper technology for its McKinley release of the IA-64/Merced processors in 2001 (2 years ahead of the roadmap).
  11. On February 7, 2000 at the ISSCC conference, IBM indicated they would have 3.3 to 4.5 GHz processors available in 2003-2004.  This is more than double the 1997 projected clock speed for this period.  See the ABC News Article and IDG Article.
  12. On September 21, 2000, Eureka Alert pointed out (here) that clever techniques for manipulating photons might allow them to be used for lithography down to l/4 instead of the more classical l/2 Rayleigh diffraction limit.  Slashdot has a discussion here.  See Boto, A. N., et. al., "Quantum Interferometric Optical Lithography: Exploiting Entanglement to Beat the Diffraction Limit",  Physical Review Letters 85(13):2733-2736 (25 Sept. 2000). When combined with a 157nm F2 laser, that would allow optical lithography to reach ~40nm (0.04mm).  If the 126nm Ar lasers become available, this could be pushed to ~32nm (0.02mm) That would seem to suggest that optical lithography may last until ~2013-2015.
  13. In December, 2000, IEEE Spectrum had an article by Darren K. Block, Elie K. Track und John M. Rowell discussing their development of circuits using RSFQ logic cooled to ~5 deg K that utilized a clock rate of 750 GHz.  News article is here (in german; use Babel Fish to translate).

Sources:

See Also:

Created: early 1998
Last Updated: June 12, 2003
HTML Editor: Robert J. Bradbury